The present invention relates to a decoding arrangement for flash memory, and more particularly, to a method of pre-charging and decoding a memory array having a plurality of bitline transistors.
Non-volatile memory (“NVM”) refers to semiconductor memory which is able to continually store information even when the supply of electricity is removed from the device containing such an NVM memory cell. Typically, NVM can be programmed with data, read and/or erased, and the programmed data can be stored for a long period of time prior to being erased. “Flash memory” is a special NVM which is an electrically erasable programmable read only memory (EEPROM) that is known in the art.
Flash memory typically stores information in an array of transistors, commonly referred to as “cells,” each of which traditionally stores one bit of information. Flash memory is based on the Floating-Gate Avalanche-Injection Metal Oxide Semiconductor (FAMOS transistor) which is essentially an n-type Metal Oxide Semiconductor (NMOS) transistor with an additional floating conductor “suspended” by insulating materials between the gate and source/drain terminals. Conventional flash memories are constructed in a cell structure wherein a single bit of information is stored in each flash memory cell. Each memory cell typically includes a MOS transistor structure having a source, a drain, and a channel in a substrate or P-well and a “stacked gate” overlying the channel. The stacked gate may further include a thin gate dielectric layer, referred to as a tunnel oxide, formed on the surface of the P-well. The stacked gate also includes a polysilicon floating gate overlying the tunnel oxide and an interpoly dielectric layer overlying the floating gate. The interpoly dielectric layer is typically a multilayer insulator such as an oxide-nitride-oxide (ONO) layer having two oxide layers sandwiching a nitride trapping layer. A polysilicon control gate normally overlies the interpoly dielectric layer, and therefore, such flash memory cells are sometimes referred to as Nitride Read Only Memory (NROM).
FIG. 1 is a cross sectional view of a conventional flash memory cell 500. The conventional floating gate flash memory cell 500 includes and n+ type source 504, a p type channel 505, an n+ type drain 512 and a p-type substrate 502. A floating gate 506 is sandwiched between an insulating dielectric layer 510 and thin tunnel oxide layer 514 over the channel 505. The floating gate 506 provides the memory storage element for the flash memory cell 500 and is electrically insulated from other elements of the memory cell 500 by the thin tunnel oxide layer 514 and the insulating dielectric layer 510. Control gate 508 is located on top of the insulating dielectric layer 510 and is positioned over the floating gate or nitride trapping layer 506. The floating gate 506 is electrically isolated from the control gate 508 by the insulating layer 510 such as a layer of silicon dioxide (SiO2) or an interpoly layer such as an oxide-nitride-oxide (ONO) interpoly oxide 510. The conventional flash memory cell 500 shown is basically an n-channel transistor with the addition of a floating gate 506. Electrical “access” or coupling to the floating gate 506 takes place only through a capacitor network of surrounding SiO2 layers and source 504, drain 512, channel 505, and control gate 508. Any charge present on the floating gate 506 is retained due to the inherent Si—SiO2 energy barrier height, thereby creating a non-volatile memory.
FIG. 2 schematically depicts a conventional array 520 of memory cells 500 diagrammatically showing a conventional read method. The memory cells 500 are generally arranged in a grid on the substrate 502. Wordlines WL0-WL31 are connected to the gates 508 each of the memory cells 500 in each row. Bitlines MBL0-MBL5 are selectively coupled to the source or drain of each of the memory cells 500 in each column. Control transistors SEL0-SEL1 select a path for programming, reading or erasing a particular cell 500 on a particular bitline MBL0-MBL5 and wordline WL0-WL31.
Programming a flash memory cell 500 means that charge (i.e., electrons) is added to the floating gate 506. A high drain to source or source to drain bias voltage is applied along with a high control gate voltage Vg. The control gate voltage Vg inverts the channel 505, while the bias accelerates electrons toward the drain 512 or source 514. In the process of crossing the channel 505, some electrons collide with the silicon lattice and become redirected toward the Si—SiO2 interface. With the aid of the field produced by the gage voltage Vg some of the electrons travel across the thin oxide layer 514 and become added to the floating gate 506. The resulting high electric field across the tunnel oxide 514 leads to a phenomena called “Fowler-Nordheim” tunneling (“FN tunneling”). Electrons in the cell channel region 505 tunnel through the gate oxide 514 into the floating gate 506 and become “trapped” in the floating gate 506 since the floating gate 506 is surrounded by the interpoly dielectric layer 510 and the tunnel oxide 514. After programming is completed the electrons added to the floating gate 506 increase the cell's threshold voltage. This change in the threshold voltage, and thereby the channel conductance, of the cell 500 created by the trapped electrons is what causes the cell 500 to be programmed.
Programming is selectively performed on each individual cell 500 in the array 520 of memory cells 500. An individual flash cell 500 is selected via its respective wordline WL0-WL31 (FIG. 2) and a pair of bitlines MBL0-MBL5 bounding the associated cell 500. A virtual ground is formed by selectively switching to ground the bitline MBL0-MBL4 associated with the source terminal 504 of only those selected flash cells 500 which are to be programmed or read.
Reading a flash memory cell 500 is performed using a sense amplifier (not shown in FIG. 2). For cells 500 that have been programmed, the turn-on voltage Vt of cells is increased by the increased charge on the floating gate 500. By applying a control gate voltage Vg and monitoring the drain current, differences between a cell 500 with charge and a cell 500 without charge on the respective floating gates 506 can be determined. A sense amplifier compares cell drain current with that of a reference cell such as a flash memory cell 500 which is programmed to the reference level during a manufacturing test. An erased memory cell 500 has more cell current than the reference cell and therefore is a logical “1” whereas a programmed memory cell 500 draws less current that the reference cell and is a logical “0.”
Erasing a flash memory cell 500 means that electrons (charge) are removed from the floating gate 506. Erasing flash memory is performed by applying electrical voltages to many cells at once so that the memory cells 500 are erased in a “flash.” A typical erase operation in a flash memory cell 500 may be performed by applying a positive voltage to the source 504, a negative or a ground voltage to the control gate 508 and holding substrate 502 of the flash memory cells 500 at ground potential. The drain 512 is allowed to “float.” Under these conditions, a high electric field is present between the floating gate 506 and the source 504. The source junction experiences a gated-diode condition during erase and electrons that manage to tunnel through the first few angstroms of the SiO2 of the tunnel oxide layer 514 are then swept into the source 504. After the erase operation has been completed, electrons have been removed from the floating gate 506 thereby reducing the cell threshold voltage Vt. While programming is selective to each individual flash memory cell 500, an erase operation typically includes many flash memory cells 500 in an array 520 being erased simultaneously.
Programming, reading and erasing flash memory cells 500 in a memory array is accomplished by a combination of bitlines and wordlines. Bitline and wordline transistors control voltage and current flow to particular memory cells 500 via the bitlines and wordlines and allow other bitlines to discharge during program, read and erase operations.
It is desirable to improve the read speed of NROM cells using a pre-charge method. It is also desirable to reduce power consumption and noise during decoding changeover by avoiding power changes during decoding changeover. It is desirable to use about Vcc/n as the pre-charge voltage, wherein n is greater than 1.